1. Field of the Invention
The present invention generally relates to a method for fabricating devices on semiconductor substrates. More specifically, the present invention relates to a method for fabricating a gate structure of a field effect transistor.
2. Description of the Related Art
Ultra-large-scale integrated (ULSI) circuits typically include more than one million transistors that are formed on a semiconductor substrate and cooperate to perform various functions within an electronic device. The transistors generally are complementary metal-oxide-semiconductor (CMOS) field effect transistors comprising a gate structure disposed between a source region and a drain region that are formed in the semiconductor substrate. The gate structure comprises a gate electrode and a gate dielectric. The gate electrode is provided over the gate dielectric and controls a flow of charge carriers in a channel region formed between the drain and the source regions to turn the transistor on or off. There is a constant trend to reduce a width of the channel region, as well as the width of the gate structure, to thereby increase the overall speed of the transistor.
The advanced CMOS transistors generally utilize polysilicon gate electrodes formed upon a gate dielectric fabricated of very thin layers of hafnium dioxide (HfO2), HfSiO2, Al2O3, ZrO2, barium strontium titanate (BST), lead zirconate titanate (PZT), ZrSiO2, HfSiON, or TaO2. Such materials have a high dielectric constant that is greater than 4.0 and are referred to as high-K materials.
To form a transistor, regions in the substrate are doped to form source and drain regions. A high K dielectric is deposited over the substrate. Polysilicon is then deposited over the dielectric layer and the polysilicon is then annealed at a high temperature. Typically, a photoresist mask may be used to pattern the gate structure. However, some high K dielectric materials can only be etched at high temperatures. The temperatures can be high enough to cause the photoresist material to reticulate. As such, in high temperature applications, a layer of silicon dioxide (SiO2) is deposited over the polysilicon and a photoresist layer is deposited over the SiO2. The photoresist layer is patterned and the SiO2 is etched to form a hard mask. The photoresist material is then removed. The SiO2 mask is used while etching the gate dielectric and removed thereafter. However, silicon dioxide has very poor selectivity with respect to polysilicon in fluorine-based cleaning chemistries. As such, when a cleaning process is activated, the mask is substantially eroded.
Therefore, there is a need in the art for a method for fabricating a gate structure of a field effect transistor using materials that are compatible with high temperatures and broad spectrum of chemistries.
The present invention is a method of fabricating a gate structure of a field effect transistor using an amorphous carbon mask. The method comprises processes of forming an xcex1-carbon mask (i.e., mask that is formed from inorganic amorphous carbon) to define the gate structure, plasma etching a gate electrode and a gate dielectric using the xcex1-carbon mask, and removing the xcex1-carbon mask after the gate structure is formed. In one embodiment, the gate dielectric comprises at least one material layer having a dielectric constant greater than 4, e.g., hafnium dioxide (HfO2), HfSiO2, alumina (Al2O3), and the like.